Advances in semiconductor processing, design and device performance coupled with dramatic reductions in manufacturing costs have created opportunities for digital technologies to invade new and previously unrelated industries. For example, in the signal processing arena, a shift is underway from analog media, such as composite television signals, to precisely calculated digital representations like high-definition TV and compact discs. As a result, a premium has been placed on the underlying hardware systems that format, manipulate, transmit and resolve such signals.
Digital data, in particular picture images, such as GIF, JPEG and MPEG images, video images for film industry, video images for video games, etc., must be processed on the order of microseconds in order to appear as a "real time image" to the viewer. Interactive enhanced-definition televisions may have decoder boxes for broadcast on demand in the home. Digitally compressed cable television systems will offer ten times the number of current channels. On-line access to databases, video games and libraries through personal computers, cable lines and telephone will dramatically enhance availability of information.
Digital Signal Processors ("DSPs") and Field Programmable Gate Arrays ("FPGA") are typical of the types of devices being used for processing digitally encoded signals. DSPs are designed to process information in real time using built in computational units. A DSP is arranged to decrease processing time by limiting execution of complicated procedures in the control application software instructions and spending most of the processing resources on resolving, decoding and communicating the incoming digital signal. The DSP is considered to be a suitable "real time" signal processor for most applications, but may be unsuitable as a general purpose real time signal processor for many of today's highly complex digital signal patterns. For high bandwidth signals, such as uncompressed video, a DSP is often inadequate.
On the other hand, a FPGA is a versatile integrated circuit chip which often includes an array of identical logic blocks. The internal circuitry of a FPGA can be configured by an individual user to realize an application specific integrated circuit ("ASIC"). During configuration, the user specifies the on-chip interconnect structure of the FPGA. The resulting arrangement is a logic circuit that is suited for a given task or function. The core logic, however, remains the same regardless of its application, resulting in a device with less than ideal performance characteristics in terms of efficiency and throughput. Thus, although FPGAs are flexible as programmable application driven devices, they lack the efficiency and processing speed required to handle complex image processing algorithms.
An integrated circuit architecture that can be configured at the mathematical operation level (addition/subtraction/multiplication/comparison) rather than at the boolean logic level (and/or/xor/invert) would provide tremendous advantages over prior art DSP and FPGA technologies. FPGAs are made up of thousands or hundreds of thousands of cells programmed or configured at the gate level using basic and/or boolean logic circuits. This means that a single multiplication operation can represent thousands of boolean operations. With a FPGA, mathematical constructs are not built in for efficiency since it is intended to provide a general purpose logic processor. Many of today's video and digital data standards require high degrees of resolution and on-the-fly reconfigurability. In image processing, for example, the image itself may be a two dimensional array of values called pixels. Current DSP and FPGA technologies, however, are two slow or consume undesirable amounts of circuitry to achieve real time processing of the incoming data stream. As data throughput demands continue to increase, the need for more flexible device architectures also increases. One approach is to couple core logics into parallel arrangements for processing the data in piece-meal fashion. Systems employing parallel processing techniques present obstacles to systems operators due to complexities inherent in configuration, setup and interface to outside systems. Parallel processors are often difficult to configure and require specialized knowledge both at the devices and system level to achieve smooth interoperability with external subsystems.
What is needed is a device architecture that provides the real time signal processing capability with internal reconfigurability functions suitable for handling today's high bandwidth digital signal formats such as compressed video, audio, compact disk, digital versatile disc and mixed mode, among others.